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? freescale semiconductor, inc., 2004, 2005, 2006, 2007. all rights reserved. freescale semiconductor data sheet: technical data dsp56374 rev. 4.2, 1/2007 table of contents 1 overview the dsp56374 is a high-density cmos device with 3.3 v inputs and outputs. note this document contains information on a new product. specifications and information herein are subject to change without notice. for software or simulation models (for example, ibis files), contact sales or go to www.freescale.com. the dsp56374 supports digital audio applications requiring sound field proce ssing, acoustic equalization, and other digital audio algorithms. the dsp56374 uses the high performance, single-clock-per-cycle dsp56300 core family of programmable cmos digital signal processors (dsps) combined with the audio signal processing capability of th e freescale semiconductor, inc. symphony? dsp family, as shown in figure 1 . significant architectural enha ncements include a barrel shifter, 24-bit addressing, and direct memory access 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 signal groupings . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . 25 6 power requirements . . . . . . . . . . . . . . . . . . . . . 26 7 thermal characteristics . . . . . . . . . . . . . . . . . . . 27 8 dc electrical characteristics . . . . . . . . . . . . . . . 28 9 ac electrical characteristics. . . . . . . . . . . . . . . . 29 10 internal clocks . . . . . . . . . . . . . . . . . . . . . . . . . . 29 11 external clock operation . . . . . . . . . . . . . . . . . . 29 12 reset, stop, mode select, and interrupt timing . 32 13 serial host interface spi protocol timing. . . . . . 35 14 serial host interface (shi) i 2 c protocol timing . 41 15 programming the serial clock . . . . . . . . . . . . . . 43 16 enhanced serial audio interface timing. . . . . . . 44 17 timer timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 18 gpio timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 19 jtag timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 20 watchdog timer timing . . . . . . . . . . . . . . . . . . . 53 dsp56374 data sheet
dsp56374 data sheet, rev. 4.2 overview freescale semiconductor 2 (dma). the dsp56374 offers 150 million instructions per second (mips) using an internal 150 mhz clock. data sheet conventions this data sheet uses the following conventions: overbar used to indicate a signal that is active when pulled low (for example, the reset pin is active when low.) ?asserted? means that a high true (active high) signal is high or that a low true (active low) signal is low ?deasserted? means that a high true (active high) signal is low or that a low true (active low) signal is high examples: signal/ symbol logic state signal state voltage* pin true asserted v il / v ol pin false deasserted v ih / v oh pin true asserted v ih / v oh pin false deasserted v il / v ol note: *values for v il , v ol , v ih , and v oh are defined by individual product specifications.
features dsp56374 data sheet, rev. 4.2 freescale semiconductor 3 figure 1. dsp56374 block diagram 2features 2.1 dsp56300 modular chassis ? 150 million instructions per second (mips) with a 150 mhz clock at an internal logic supply (qvddl) of 1.25 v ? object code compatible with the 56k core ? data alu with a 24 x 24 bit multiplier-accumulato r and a 56-bit barrel shifter;16 bit arithmetic support ? program control with position independent code support pll once clock gen. yab xab pab ydb xdb pdb gdb modb/irqb/gpio modc/irqc/gpio dsp56300 12 24-bit ddb dab peripheral core ym_eb xm_eb pm_eb pio_eb expansion area jtag 4 5 reset moda/irqa/gpio pinit/nmi extal address generation unit six channel dma unit program interrupt controller program decode controller program address generator data alu 24 24 + 56 56-bit mac two 56-bit accumulators 56-bit barrel shifter power mgmt. memory expansion area x data ram 6k 24 y data ram 6k 24 bootstrap rom internal data bus switch shi gpio esai esai_1 interface interface interface 12* 15* triple 3 rom 4k 24 rom 4k 24 program ram 6k 24 rom 20k 24 xtal modd/irqd/gpio timer watch dog timer * esai_1 and dedicated gpio pins are not available in the 52-pin package.
dsp56374 data sheet, rev. 4.2 features freescale semiconductor 4 ? six-channel dma controller ? provides a wide range of freque ncy multiplications (1 to 255), pr edivider factors (1 to 31), pll feedback multiplier (2 or 4), output divide fact or (1, 2, or 4) and a power-saving clock divider (2 i : i = 0 to 7) to reduce clock noise ? internal address tracing support and once for hardware/software debugging ? jtag port, supporting boundary scan, compliant to ieee 1149.1 ? very low-power cmos design, fully static design with operating frequencies down to dc ? stop and wait low-power standby modes 2.2 on-chip memory configuration ? 6kx24 bit y-data ram a nd 4kx24 bit y-data rom ? 6kx24 bit x-data ram a nd 4kx24 bit x-data rom ? 20kx24 bit program and bootstrap rom including a prom patching mechanism ? 6kx24 bit program ram. ? various memory switches are ava ilable. see memory table below. 2.3 peripheral m odules ? enhanced serial audio interface (esai): up to 4 receiver pins and up to 6 transmitter pins, master or slave. i 2 s, sony, ac97, network, and other programmable protocols. ? enhanced serial audio interface i (esai_1): up to 4 receiver pins and up to 6 transmitter pins, master or slave. i 2 s, sony, ac97, network and ot her programmable protocols. note: available in the 80-pin package only. ? serial host interface (shi): spi and i 2 c protocols, 10-word receive fifo, support for 8, 16, and 24-bit words. three noise reduction filter modes. ? triple timer module (tec) ? most pins of unused peripherals may be programmed as gpio pins. up to 47 pins can be configured as gpio on the 80 pin package and 20 pins on the 52 pin package. table 1. dsp56374 memory switch configurations bit settings memory sizes (24-bit words) msw1 msw0 ms prog ram x data ram y data ram prog rom x data rom y data rom x x 0 6k 6k 6k 20k 4k 4k 0 0 1 2k 10k 6k 20k 4k 4k 0 1 1 4k 8k 6k 20k 4k 4k 1 0 1 8k 4k 6k 20k 4k 4k 1 1 1 10k 4k 4k 20k 4k 4k
documentation dsp56374 data sheet, rev. 4.2 freescale semiconductor 5 ? hardware watchdog timer 2.4 packages 80-pin and 52-pin plastic lqfp packages. 3 documentation table 2 lists the documents that provide a complete de scription of the dsp56374 and are required to design properly with the part. documentation is available fr om a local freescale semiconductor, inc. (formerly motorola) distributor, semiconductor sa les office, literature distribution center, or through the freescale dsp home page on the internet (the s ource for the latest information). 4 signal groupings the input and output signals of the dsp56374 are orga nized into functional groups, which are listed in table 3. the dsp56374 is operated from a 1.25 v and 3.3 v supply; however, some of the inputs can tolerate 5.0 v. a special notice for this feature is added to the signal descriptions of those inputs. table 2. dsp56374 documentation document name description order number dsp56300 family manual detailed description of the 56300-family architecture and the 24-bit core processor and instruction set dsp56300fm/ad dsp56374 user?s manual detailed description of memory, peripherals, and interfaces dsp56374um/d dsp56374 technical data sheet electrical and timing specifications; pin and package descriptions dsp56374 dsp56374 product brief brief description of the chip dsp56374pb/d table 3. dsp56374 functional signal groupings functional group number of signals 1 detailed description power (v dd )11 table 15 ground (gnd) 9 ta bl e 5 scan pins 1 ta bl e 6 clock and pll 3 ta bl e 7 interrupt and mode control port h 2 5 ta bl e 8 shi port h 2 5 ta bl e 9 esai port c 4 12 table 10 esai_1 port e 5 12 table 11
dsp56374 data sheet, rev. 4.2 signal groupings freescale semiconductor 6 4.1 power 4.2 ground dedicated gpio port g 3 15 table 12 timer 3 table 13 jtag/once port 4 table 14 note: 1 pins are not 5 v. tolerant unless noted. 2 port h signals are the gpio port signals which are multiplexed with the mod and hreq signals. 3 port g signals are the dedicated gpio port signals. 4 port c signals are the gpio port signals which are multiplexed with the esai signals. 5 port e signals are the gpio port signals which are multiplexed with the esai_1 signals. table 4. power inputs power name description plla_vdd (1) pll power? the voltage (3.3 v) should be well-regulated and the input should be provided with an extremely low impedance path to the 3.3 v dd power rail. the user must provide adequate external decoupling capacitors between plla_vdd and plla_gnd. plla_vdd requires a filter as shown in figure 1 and figure 2 below. see the dsp56374 technical data sheet for additional details. pllp_vdd(1) pll power? the voltage (3.3 v) should be well-regulated and the input should be provided with an extremely low impedance path to the 3.3 v dd power rail. the user must provide adequate external decoupling capacitors between pllp_vdd and pllp_gnd. plld_vdd (1) pll power? the voltage (1.25 v) should be well-regulated and the input should be provided with an extremely low impedance path to the 1.25 v dd power rail. the user must provide adequate external decoupling capacitors between plld_vdd and plld_gnd. core_vdd (4) core power?the voltage (1.25 v) should be well-regulated and the input should be provided with an extremely low impedance path to the 1.25 v dd power rail. the user must provide adequate external decoupling capacitors. io_vdd (80-pin 4) (52-pin 3) shi, esai, esai_1, wdt and timer i/o power ?the voltage (3.3 v) should be well-regulated, and the input should be provided with an extremely low impedance path to the 3.3 v dd power rail. this is an isolated power for the shi, esai, esai_1, wdt and timer i/o. the user must provide adequate external decoupling capacitors. table 5. grounds ground name description plla_gnd(1) pll ground?the pll ground should be provided with an extremely low-impedance path to ground. this connection must be tied externally to all other chip ground connections. the user must provide adequate external decoupling capacitors between plla_vdd and plla_gnd. table 3. dsp56374 functional signal groupings (continued) functional group number of signals 1 detailed description
signal groupings dsp56374 data sheet, rev. 4.2 freescale semiconductor 7 4.3 scan 4.4 clock and pll pllp_gnd(1) pll ground?the pll ground should be provided with an extremely low-impedance path to ground. this connection must be tied externally to all other chip ground connections. the user must provide adequate external decoupling capacitors between pllp_vdd and pllp_gnd. plld_gnd(1) pll ground?the pll ground should be provided with an extremely low-impedance path to ground. this connection must be tied externally to all other chip ground connections. the user must provide adequate external decoupling capacitors between plld_vdd and plld_gnd. core_gnd(4) core ground?the core ground should be provided with an extremely low-impedance path to ground. this connection must be tied externally to all other chip ground connections. the user must provide adequate external decoupling capacitors. io_gnd(2) shi, esai, esai_1, wdt and timer i/o ground?io_gnd is the ground for the shi, esai, esai_1, wdt and timer i/o. this connection must be tied externally to all other chip ground connections. the user must provide adequate external decoupling capacitors. table 6. scan signals signal name type state during reset signal description scan input input scan?manufacturing test pin. this pin must be connected to ground. table 7. clock and pll signals signal name type state during reset signal description extal input input external clock / crystal input?an external clock source must be connected to extal in order to supply the clock to the internal clock generator and pll. xtal output chip driven crystal output?connects the internal crystal oscillator output to an external crystal. if an external clock is used, leave xtal unconnected. pinit/nmi input input pll initial/nonmaskable interrupt?during assertion of reset , the value of pinit/nmi is written into the pll enable (pen) bit of the pll control register, determining whether the pll is enabled or disabled. after reset de-assertion and during normal instruction processing, the pinit/nmi schmitt-trigger input is a negative-edge-triggered nonmaskable interrupt (nmi) request internally synchronized to the internal system clock. this pin has an internal pull up resistor. this input is 5 v tolerant. table 5. grounds (continued) ground name description
dsp56374 data sheet, rev. 4.2 signal groupings freescale semiconductor 8 4.5 interrupt and mode control the interrupt and mode control signals select the chip ?s operating mode as it come s out of hardware reset. after reset is de-asserted, these inputs are hardware interrupt request lines. table 8. interrupt and mode control signal name type state during reset signal description moda/irqa input moda input mode select a/external interrupt request a?moda/irqa is an active-low schmitt-trigger input, internally synchronized to the dsp clock. moda/irqa selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. this pin can also be programmed as gpio. moda, modb, modc, and modd select one of 16 initial chip operating modes, latched into the omr when the reset signal is de-asserted. if the processor is in the stop standby state and the moda/irqa pin is pulled to gnd, the processor will exit the stop state. this pin has an internal pull up resistor. this input is 5 v tolerant. ph0 input, output, or disconnected port h0?when the moda/irqa is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. modb/irqb input modb input mode select b/external interrupt request b?modb/irqb is an active-low schmitt-trigger input, internally synchronized to the dsp clock. modb/irqb selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. this pin can also be programmed as gpio. moda, modb, modc, and modd select one of 16 initial chip operating modes, latched into omr when the reset signal is de-asserted. this pin has an internal pull up resistor. this input is 5 v tolerant. ph1 input, output, or disconnected port h1?when the modb/irqb is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. modc/irqc input modc input mode select c/external interrupt request c?modc/irqc is an active-low schmitt-trigger input, internally synchronized to the dsp clock. modc/irqc selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. this pin can also be programmed as gpio. moda, modb, modc, and modd select one of 16 initial chip operating modes, latched into omr when the reset signal is de-asserted. this pin has an internal pull up resistor. this input is 5 v tolerant.
signal groupings dsp56374 data sheet, rev. 4.2 freescale semiconductor 9 4.6 serial host interface the shi has five i/o signals that can be configured to allow the shi to operate in either spi or i 2 c mode. ph2 input, output, or disconnected port h2?when the modc/irqc is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. modd/irqd input modd input mode select d/external interrupt request d?modd/irqd is an active-low schmitt-trigger input, internally synchronized to the dsp clock. modd/irqd selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. this pin can also be programmed as gpio. moda, modb, modc, and modd select one of 16 initial chip operating modes, latched into omr when the reset signal is de-asserted. this pin has an internal pull up resistor. this input is 5 v tolerant. ph3 input, output, or disconnected port h3?when the modd/irqd is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. reset input input reset?reset is an active-low, schmitt-trigger input. when asserted, the chip is placed in the reset state and the internal phase generator is reset. the schmitt-trigger input allows a slowly rising input (such as a capacitor charging) to reset the chip reliably. when the reset signal is de-asserted, the initial chip operating mode is latched from the moda, modb, modc, and modd inputs. the reset signal must be asserted during power up. a stable extal signal must be supplied while reset is being asserted. this pin has an internal pull up resistor. this input is 5 v tolerant. table 8. interrupt and mode control (continued) signal name type state during reset signal description
dsp56374 data sheet, rev. 4.2 signal groupings freescale semiconductor 10 table 9. serial host interface signals signal name signal type state during reset signal description sck input or output tri-stated spi serial clock?the sck signal is an output when the spi is configured as a master and a schmitt-trigger input when the spi is configured as a slave. when the spi is configured as a master, the sck signal is derived from the internal shi clock generator. when the spi is configured as a slave, the sck signal is an input, and the clock signal from the external master synchronizes the data transfer. the sck signal is ignored by the spi if it is defined as a slave and the slave select (ss ) signal is not asserted. in both the master and slave spi devices, data is shifted on one edge of the sck signal and is sampled on the opposite edge where data is stable. edge polarity is determined by the spi transfer protocol. scl input or output i 2 c serial clock?scl carries the clock for i 2 c bus transactions in the i 2 c mode. scl is a schmitt-trigger input when configured as a slave and an open-drain output when configured as a master. scl should be connected to v dd through an external pull-up resistor according to the i 2 c specifications. this signal is tri-stated during hardware, software, and individual reset. this pin has an internal pull up resistor. this input is 5 v tolerant. miso input or output tri-stated spi master-in-slave-out?when the spi is configured as a master, miso is the master data input line. the miso signal is used in conjunction with the mosi signal for transmitting and receiving serial data. this signal is a schmitt-trigger input when configured for the spi master mode, an output when configured for the spi slave mode, and tri-stated if configured for the spi slave mode when ss is de-asserted. an external pull-up resistor is not required for spi operation. sda input or open-drain output i 2 c data and acknowledge?in i 2 c mode, sda is a schmitt-trigger input when receiving and an open-drain output when transmitting. sda should be connected to v dd through a pull-up resistor. sda carries the data for i 2 c transactions. the data in sda must be stable during the high period of scl. the data in sda is only allowed to change when scl is low. when the bus is free, sda is high. the sda line is only allowed to change during the time scl is high in the case of start and stop events. a high-to-low transition of the sda line while scl is high is a unique situation, and is defined as the start event. a low-to-high transition of sda while scl is high is a unique situation defined as the stop event. this signal is tri-stated during hardware, software, and individual reset. thus, there is no need for an external pull-up in this state. this pin has an internal pull up resistor. this input is 5 v tolerant.
signal groupings dsp56374 data sheet, rev. 4.2 freescale semiconductor 11 mosi input or output tri-stated spi master-out-slave-in?when the spi is configured as a master, mosi is the master data output line. the mosi signal is used in conjunction with the miso signal for transmitting and receiving serial data. mosi is the slave data input line when the spi is configured as a slave. this signal is a schmitt-trigger input when configured for the spi slave mode. ha0 input i 2 c slave address 0?this signal uses a schmitt-trigger input when configured for the i 2 c mode. when configured for i 2 c slave mode, the ha0 signal is used to form the slave device address. ha0 is ignored when configured for the i 2 c master mode. this signal is tri-stated during hardware, software, and individual reset. thus, there is no need for an external pull-up in this state. this pin has an internal pull up resistor. this input is 5 v tolerant. ss input ignored input spi slave select?this signal is an active low schmitt-trigger input when configured for the spi mode. when configured for the spi slave mode, this signal is used to enable the spi slave for transfer. when configured for the spi master mode, this signal should be kept de-asserted (pulled high). if it is asserted while configured as spi master, a bus error condition is flagged. if ss is de-asserted, the shi ignores sck clocks and keeps the miso output signal in the high-impedance state. ha2 input i 2 c slave address 2?this signal uses a schmitt-trigger input when configured for the i 2 c mode. when configured for the i 2 c slave mode, the ha2 signal is used to form the slave device address. ha2 is ignored in the i 2 c master mode. this pin has an internal pull up resistor. this input is 5 v tolerant. hreq ph4 input or output input, output, or disconnected tri-stated host request?this signal is an active low schmitt-trigger input when configured for the master mode but an active low output when configured for the slave mode. when configured for the slave mode, hreq is asserted to indicate that the shi is ready for the next data word transfer and de-asserted at the first clock pulse of the new data word transfer. when configured for the master mode, hreq is an input. when asserted by the external slave device, it will trigger the start of the data word transfer by the master. after finishing the data word transfer, the master will await the next assertion of hreq to proceed to the next transfer. this pin can also be programmed as gpio. port h4?when hreq is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. this pin has an internal pull up resistor. this input is 5 v tolerant. table 9. serial host interface signals (continued) signal name signal type state during reset signal description
dsp56374 data sheet, rev. 4.2 signal groupings freescale semiconductor 12 4.7 enhanced serial audio interface table 10. enhanced serial audio interface signals signal name signal type state during reset signal description hckr input or output gpio disconnected high frequency clock for receiver?when programmed as an input, this signal provides a high frequency clock source for the esai receiver as an alternate to the dsp core clock. when programmed as an output, this signal can serve as a high-frequency sample clock (e.g., for external digital to analog converters [dacs]) or as an additional system clock. pc2 input, output, or disconnected port c2?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after reset is gpio disconnected. this pin has an internal pull up resistor. this input is 5 v tolerant. hckt input or output gpio disconnected high frequency clock for transmitter?when programmed as an input, this signal provides a high frequency clock source for the esai transmitter as an alternate to the dsp core clock. when programmed as an output, this signal can serve as a high frequency sample clock (e.g., for external dacs) or as an additional system clock. pc5 input, output, or disconnected port c5?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after reset is gpio disconnected. this pin has an internal pull up resistor. this input is 5 v tolerant.
signal groupings dsp56374 data sheet, rev. 4.2 freescale semiconductor 13 fsr input or output gpio disconnected frame sync for receiver?this is the receiver frame sync input/output signal. in the asynchronous mode (syn=0), the fsr pin operates as the frame sync input or output used by all the enabled receivers. in the synchronous mode (syn=1), it operates as either the serial flag 1 pin (tebe=0), or as the transmitter external buffer enable control (tebe=1, rfsd=1). when this pin is configured as serial flag pin, its direction is determined by the rfsd bit in the rccr register. when configured as the output flag of1, this pin will reflect the value of the of1 bit in the saicr register, and the data in the of1 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. when configured as the input flag if1, the data value at the pin will be stored in the if1 bit in the saisr register, synchronized by the frame sync in normal mode or the slot in network mode. pc1 input, output, or disconnected port c1?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after reset is gpio disconnected. internal pull down resistor. this input is 5 v tolerant. fst input or output gpio disconnected frame sync for transmitter?this is the transmitter frame sync input/output signal. for synchronous mode, this signal is the frame sync for both transmitters and receivers. for asynchronous mode, fst is the frame sync for the transmitters only. the direction is determined by the transmitter frame sync direction (tfsd) bit in the esai transmit clock control register (tccr). pc4 input, output, or disconnected port c4?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after reset is gpio disconnected. internal pull down resistor. this input is 5 v tolerant. table 10. enhanced serial audio interface signals (continued) signal name signal type state during reset signal description
dsp56374 data sheet, rev. 4.2 signal groupings freescale semiconductor 14 sckr input or output gpio disconnected receiver serial clock?sckr provides the receiver serial bit clock for the esai. the sckr operates as a clock input or output used by all the enabled receivers in the asynchronous mode (syn=0), or as serial flag 0 pin in the synchronous mode (syn=1). when this pin is configured as serial flag pin, its direction is determined by the rckd bit in the rccr register. when configured as the output flag of0, this pin will reflect the value of the of0 bit in the saicr register, and the data in the of0 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. when configured as the input flag if0, the data value at the pin will be stored in the if0 bit in the saisr register, synchronized by the frame sync in normal mode or the slot in network mode. pc0 input, output, or disconnected port c0?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after reset is gpio disconnected. internal pull down resistor. this input is 5 v tolerant. sckt input or output gpio disconnected transmitter serial clock?this signal provides the serial bit rate clock for the esai. sckt is a clock input or output used by all enabled transmitters and receivers in synchronous mode, or by all enabled transmitters in asynchronous mode. pc3 input, output, or disconnected port c3?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after reset is gpio disconnected. internal pull down resistor. this input is 5 v tolerant. table 10. enhanced serial audio interface signals (continued) signal name signal type state during reset signal description
signal groupings dsp56374 data sheet, rev. 4.2 freescale semiconductor 15 sdo5 output gpio disconnected serial data output 5?when programmed as a transmitter, sdo5 is used to transmit data from the tx5 serial transmit shift register. sdi0 input serial data input 0?when programmed as a receiver, sdi0 is used to receive serial data into the rx0 serial receive shift register. pc6 input, output, or disconnected port c6?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after reset is gpio disconnected. internal pull down resistor. this input is 5 v tolerant. sdo4 output gpio disconnected serial data output 4?when programmed as a transmitter, sdo4 is used to transmit data from the tx4 serial transmit shift register. sdi1 input serial data input 1?when programmed as a receiver, sdi1 is used to receive serial data into the rx1 serial receive shift register. pc7 input, output, or disconnected port c7?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after reset is gpio disconnected. internal pull down resistor. this input is 5 v tolerant. sdo3 output gpio disconnected serial data output 3 ?when programmed as a transmitter, sdo3 is used to transmit data from the tx3 serial transmit shift register. sdi2 input serial data input 2 ?when programmed as a receiver, sdi2 is used to receive serial data into the rx2 serial receive shift register. pc8 input, output, or disconnected port c8?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after reset is gpio disconnected. internal pull down resistor. this input is 5 v tolerant. table 10. enhanced serial audio interface signals (continued) signal name signal type state during reset signal description
dsp56374 data sheet, rev. 4.2 signal groupings freescale semiconductor 16 sdo2 output gpio disconnected serial data output 2?when programmed as a transmitter, sdo2 is used to transmit data from the tx2 serial transmit shift register sdi3 input serial data input 3?when programmed as a receiver, sdi3 is used to receive serial data into the rx3 serial receive shift register. pc9 input, output, or disconnected port c9?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after reset is gpio disconnected. internal pull down resistor. this input is 5 v tolerant. sdo1 output gpio disconnected serial data output 1?sdo1 is used to transmit data from the tx1 serial transmit shift register. pc10 input, output, or disconnected port c10?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after reset is gpio disconnected. internal pull down resistor. this input is 5 v tolerant. sdo0 output gpio disconnected serial data output 0?sdo0 is used to transmit data from the tx0 serial transmit shift register. pc11 input, output, or disconnected port c11?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after reset is gpio disconnected. internal pull down resistor. this input is 5 v tolerant. table 10. enhanced serial audio interface signals (continued) signal name signal type state during reset signal description
signal groupings dsp56374 data sheet, rev. 4.2 freescale semiconductor 17 4.8 enhanced serial audio interface_1 table 11. enhanced serial audio interface_1 signals signal name signal type state during reset signal description hckr_1 input or output gpio disconnected high frequency clock for receiver?when programmed as an input, this signal provides a high frequency clock source for the esai_1 receiver as an alternate to the dsp core clock. when programmed as an output, this signal can serve as a high-frequency sample clock (e.g., for external digital to analog converters [dacs]) or as an additional system clock. pe2 input, output, or disconnected port e2?when the esai_1 is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after reset is gpio disconnected. internal pull down resistor. this input is 5 v tolerant. hckt_1 input or output gpio disconnected high frequency clock for transmitter?when programmed as an input, this signal provides a high frequency clock source for the esai_1 transmitter as an alternate to the dsp core clock. when programmed as an output, this signal can serve as a high frequency sample clock (e.g., for external dacs) or as an additional system clock. pe5 input, output, or disconnected port e5?when the esai_1 is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after reset is gpio disconnected. internal pull down resistor. this input is 5 v tolerant.
dsp56374 data sheet, rev. 4.2 signal groupings freescale semiconductor 18 fsr_1 input or output gpio disconnected frame sync for receiver_1?this is the receiver frame sync input/output signal. in the asynchronous mode (syn=0), the fsr_1 pin operates as the frame sync input or output used by all the enabled receivers. in the synchronous mode (syn=1), it operates as either the serial flag 1 pin (tebe=0), or as the transmitter external buffer enable control (tebe=1, rfsd=1). when this pin is configured as serial flag pin, its direction is determined by the rfsd bit in the rccr_1 register. when configured as the output flag of1, this pin will reflect the value of the of1 bit in the saicr_1 register, and the data in the of1 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. when configured as the input flag if1, the data value at the pin will be stored in the if1 bit in the saisr_1 register, synchronized by the frame sync in normal mode or the slot in network mode. pe1 input, output, or disconnected port e1?when the esai_1 is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after reset is gpio disconnected. internal pull down resistor. this input is 5 v tolerant fst_1 input or output gpio disconnected frame sync for transmitter_1?this is the transmitter frame sync input/output signal. for synchronous mode, this signal is the frame sync for both transmitters and receivers. for asynchronous mode, fst_1 is the frame sync for the transmitters only. the direction is determined by the transmitter frame sync direction (tfsd) bit in the esai_1 transmit clock control register (tccr_1). pe4 input, output, or disconnected port e4?when the esai_1 is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after reset is gpio disconnected. internal pull down resistor. this input is 5 v tolerant. table 11. enhanced serial audio interface_1 signals (continued) signal name signal type state during reset signal description
signal groupings dsp56374 data sheet, rev. 4.2 freescale semiconductor 19 sckr_1 input or output gpio disconnected receiver serial clock_1?sckr_1 provides the receiver serial bit clock for the esai_1. the sckr_1 operates as a clock input or output used by all the enabled receivers in the asynchronous mode (syn=0), or as serial flag 0 pin in the synchronous mode (syn=1). when this pin is configured as serial flag pin, its direction is determined by the rckd bit in the rccr_1 register. when configured as the output flag of0, this pin will reflect the value of the of0 bit in the saicr_1 register, and the data in the of0 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. when configured as the input flag if0, the data value at the pin will be stored in the if0 bit in the saisr_1 register, synchronized by the frame sync in normal mode or the slot in network mode. pe0 input, output, or disconnected port e0?when the esai_1 is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after reset is gpio disconnected. internal pull down resistor. this input is 5 v tolerant sckt_1 input or output gpio disconnected transmitter serial clock_1?this signal provides the serial bit rate clock for the esai_1. sckt_1 is a clock input or output used by all enabled transmitters and receivers in synchronous mode, or by all enabled transmitters in asynchronous mode. pe3 input, output, or disconnected port e3?when the esai_1 is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after reset is gpio disconnected. internal pull down resistor. this input is 5 v tolerant table 11. enhanced serial audio interface_1 signals (continued) signal name signal type state during reset signal description
dsp56374 data sheet, rev. 4.2 signal groupings freescale semiconductor 20 sdo5_1 output gpio disconnected serial data output 5_1?when programmed as a transmitter, sdo5_1 is used to transmit data from the tx5 serial transmit shift register. sdi0_1 input serial data input 0_1?when programmed as a receiver, sdi0_1 is used to receive serial data into the rx0 serial receive shift register. pe6 input, output, or disconnected port e6?when the esai_1 is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after reset is gpio disconnected. internal pull down resistor. this input is 5 v tolerant sdo4_1 output gpio disconnected serial data output 4_1?when programmed as a transmitter, sdo4_1 is used to transmit data from the tx4 serial transmit shift register. sdi1_1 input serial data input 1_1?when programmed as a receiver, sdi1_1 is used to receive serial data into the rx1 serial receive shift register. pe7 input, output, or disconnected port e7?when the esai_1 is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after reset is gpio disconnected. internal pull down resistor. this input is 5 v tolerant. sdo3_1 output gpio disconnected serial data output 3 ?when programmed as a transmitter, sdo3_1 is used to transmit data from the tx3 serial transmit shift register. sdi2_1 input serial data input 2 ?when programmed as a receiver, sdi2_1 is used to receive serial data into the rx2 serial receive shift register. pe8 input, output, or disconnected port e8?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after reset is gpio disconnected. internal pull down resistor. this input is 5 v tolerant. table 11. enhanced serial audio interface_1 signals (continued) signal name signal type state during reset signal description
signal groupings dsp56374 data sheet, rev. 4.2 freescale semiconductor 21 sdo2_1 output gpio disconnected serial data output 2?when programmed as a transmitter, sdo2_1 is used to transmit data from the tx2 serial transmit shift register. sdi3_1 input serial data input 3?when programmed as a receiver, sdi3_1 is used to receive serial data into the rx3 serial receive shift register. pe9 input, output, or disconnected port e9?when the esai_1 is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after reset is gpio disconnected. internal pull down resistor. this input is 5 v tolerant. sdo1_1 output gpio disconnected serial data output 1?sdo1_1 is used to transmit data from the tx1 serial transmit shift register. pe10 input, output, or disconnected port e10?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after reset is gpio disconnected. internal pull down resistor. this input is 5 v tolerant. sdo0_1 output gpio disconnected serial data output 0?sdo0_1 is used to transmit data from the tx0 serial transmit shift register. pe11 input, output, or disconnected port e11?when the esai_1 is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after reset is gpio disconnected. internal pull down resistor. this input is 5 v tolerant. table 11. enhanced serial audio interface_1 signals (continued) signal name signal type state during reset signal description
dsp56374 data sheet, rev. 4.2 signal groupings freescale semiconductor 22 4.9 dedicated gpio-port g table 12. dedicated gpio-port g signals signal name type state during reset signal description pg0 input, output, or disconnected gpio disconnected port g0?this signal is individually programmable as input, output, or internally disconnected. internal pull down resistor. this input is 5 v tolerant pg1 input, output, or disconnected gpio disconnected port g1?this signal is individually programmable as input, output, or internally disconnected. internal pull down resistor. this input is 5 v tolerant pg2 input, output, or disconnected gpio disconnected port g2?this signal is individually programmable as input, output, or internally disconnected. internal pull down resistor. this input is 5 v tolerant pg3 input, output, or disconnected gpio disconnected port g3?this signal is individually programmable as input, output, or internally disconnected. internal pull down resistor. this input is 5 v tolerant pg4 input, output, or disconnected gpio disconnected port g4?this signal is individually programmable as input, output, or internally disconnected. internal pull down resistor. this input is 5 v tolerant pg5 input, output, or disconnected gpio disconnected port g5?this signal is individually programmable as input, output, or internally disconnected. internal pull down resistor. this input is 5 v tolerant pg6 input, output, or disconnected gpio disconnected port g6?this signal is individually programmable as input, output, or internally disconnected. internal pull down resistor. this input is 5 v tolerant pg7 input, output, or disconnected gpio disconnected port g7?this signal is individually programmable as input, output, or internally disconnected. internal pull down resistor. this input is 5 v tolerant pg8 input, output, or disconnected gpio disconnected port g8?this signal is individually programmable as input, output, or internally disconnected. internal pull down resistor. this input is 5 v tolerant
signal groupings dsp56374 data sheet, rev. 4.2 freescale semiconductor 23 pg9 input, output, or disconnected gpio disconnected port g9?this signal is individually programmable as input, output, or internally disconnected. internal pull down resistor. this input is 5 v tolerant pg10 input, output, or disconnected gpio disconnected port g10?this signal is individually programmable as input, output, or internally disconnected. internal pull down resistor. this input is 5 v tolerant pg11 input, output, or disconnected gpio disconnected port g11?this signal is individually programmable as input, output, or internally disconnected. internal pull down resistor. this input is 5 v tolerant pg12 input, output, or disconnected gpio disconnected port g12?this signal is individually programmable as input, output, or internally disconnected. internal pull down resistor. this input is 5 v tolerant pg13 input, output, or disconnected gpio disconnected port g13?this signal is individually programmable as input, output, or internally disconnected. internal pull down resistor. this input is 5 v tolerant pg14 input, output, or disconnected gpio disconnected port g14?this signal is individually programmable as input, output, or internally disconnected. internal pull down resistor. this input is 5 v tolerant table 12. dedicated gpio-port g signals (continued) signal name type state during reset signal description
dsp56374 data sheet, rev. 4.2 signal groupings freescale semiconductor 24 4.10 timer table 13. timer signal signal name type state during reset signal description tio0 input or output gpio input timer 0 schmitt-trigger input/output?when timer 0 functions as an external event counter or in measurement mode, tio0 is used as input. when timer 0 functions in watchdog, timer, or pulse modulation mode, tio0 is used as output. the default mode after reset is gpio input. this can be changed to output or configured as a timer input/output through the timer 0 control/status register (tcsr0). if tio0 is not being used, it is recommended to either define it as gpio output immediately at the beginning of operation or leave it defined as gpio input. internal pull down resistor. this input is 5 v tolerant tio1 input or output watchdog timer output timer 1 schmitt-trigger input/output?when timer 1 functions as an external event counter or in measurement mode, tio1 is used as input. when timer 1 functions in watchdog, timer, or pulse modulation mode, tio1 is used as output. the default mode after reset is gpio input. this can be changed to output or configured as a timer input/output through the timer 1control/status register (tcsr1). if tio1 is not being used, it is recommended to either define it as gpio output immediately at the beginning of operation or leave it defined as gpio input. wdt output wdt?when this pin is configured as a hardware watchdog timer pin, this signal is asserted low when the hardware watchdog timer counts down to zero. internal pull down resistor. this input is 5 v tolerant tio2 input or output plock output timer 2 schmitt-trigger input/output?when timer 2 functions as an external event counter or in measurement mode, tio2 is used as input. when timer 2 functions in watchdog, timer, or pulse modulation mode, tio2 is used as output. the default mode after reset is gpio input. this can be changed to output or configured as a timer input/output through the timer control/status register (tcsr2). if tio2 is not being used, it is recommended to either define it as gpio output immediately at the beginning of operation or leave it defined as gpio input .
maximum ratings dsp56374 data sheet, rev. 4.2 freescale semiconductor 25 4.11 jtag/once interface 5 maximum ratings caution this device contains circuitry protecting against damage due to high static voltage or electrical fields. however, normal precautions should be taken to avoid exceeding maximum voltage ratings. reliab ility of operation is enhanced if unused inputs are pulled to an appropriate l ogic voltage level (e.g., either gnd or v dd ). the suggested value for a pullup or pulldown resistor is 4.7 k ?. plock output plock?when this pin is configured as a pll lock pin, this signal is asserted high when the on-chip pll enabled and locked and de-asserted when the pll enabled and unlocked. this pin is also asserted high when the pll is disabled. internal pull down resistor. this input is 5 v tolerant table 14. jtag/once interface signal name signal type state during reset signal description tck input input test clock?tck is a test clock input signal used to synchronize the jtag test logic. internal pull up resistor. this input is 5 v tolerant. tdi input input test data input?tdi is a test data serial input signal used for test instructions and data. tdi is sampled on the rising edge of tck. internal pull up resistor. this input is 5 v tolerant. tdo output tri-stated test data output?tdo is a test data serial output signal used for test instructions and data. tdo is tri-statable and is actively driven in the shift-ir and shift-dr controller states. tdo changes on the falling edge of tck. tms input input test mode select?tms is an input signal used to sequence the test controller?s state machine. tms is sampled on the rising edge of tck. internal pull up resistor. this input is 5 v tolerant. table 13. timer signal (continued) signal name type state during reset signal description
dsp56374 data sheet, rev. 4.2 power requirements freescale semiconductor 26 note in the calculation of timing requireme nts, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. a maximum specification is calculated using a worst case variation of process parameter values in one direction. the minimum specification is calculated using the worst case for the same parameters in the opposite direction. therefore, a ?maximum? value for a specification will never occur in the same device that has a ?minimum? value for a nother specification; adding a maximum to a minimum represents a condition that can never exist. 6 power requirements to prevent high current conditions due to possibl e improper sequencing of the power supplies, the connection shown below is recommended to be made between the dsp56374 io_vdd and core_vdd power pins. table 15. maximum ratings rating 1 symbol value 1, 2 unit supply voltage v core_vdd, v plld_vdd ? 0.3 to + 1.6 v v pllp_vdd, v io_vdd, v plla_vdd , ? 0.3 to + 4.0 v maximum core_vdd power supply ramp time 4 tr 1 0 m s all ?5.0v tolerant? input voltages v in gnd ? 0.3 to 6v v current drain per pin excluding v dd and gnd(except for pads listed below) i12ma sck_scl i sck 16 ma tdo i jtag 24 ma operating temperature range 3 t j 80 lqfp = 105 52 lqfp = 110 c storage temperature t stg ? 55 to +125 c esd protected voltage (human body model) 2000 v esd protected voltage (machine model) 200 v note: 1 gnd = 0 v, t j = -40c to 110c (52 lqfp) / -40c to 105c (80 lqfp), cl = 50pf 2 absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. stress beyond the maximum rating may affect device reliability or cause permanent damage to the device. 3 operating temperature qualified for automotive applications. t j = t a + ja x power. variables used were core current = 100 ma, i/o current = 60 ma, core voltage = 1.3 v, i/o voltage = 3.46 v, t a = 85c 4 if the power supply ramp to full supply time is longer than 10 ms, the por circuitry will not operate correctly, causing erroneous operation.
thermal characteristics dsp56374 data sheet, rev. 4.2 freescale semiconductor 27 to prevent a high current condition upon power up, the io_vdd must be applied ahead of the core_vdd as shown below if the external schottky is not used. for correct operation of the internal power on reset logic, the core_vdd ramp rate (tr) to full supply must be less than 10 ms. this is shown below. 7 thermal characteristics table 16. thermal characteristics characteristic symbol lqfp values unit natural convection, junction-to-ambient thermal resistance 1,2 r ja or ja 68 (52 lqfp) 50 (80 lqfp) c/w junction-to-case thermal resistance 3 r jc or jc 17 (52 lqfp) 11 (80 lqfp) c/w note: 1 junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2 per semi g38-87 and jedec jesd51-2 with the single layer board horizontal. 3 thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1). io_vdd core_vdd external schottky diode core_vdd io_vdd core_vdd tr 0 v 1.25 v
dsp56374 data sheet, rev. 4.2 dc electrical characteristics freescale semiconductor 28 8 dc electrical characteristics table 17. dc electrical characteristics characteristics symbol min typ max unit supply voltages core (core_vdd) pll (plld_vdd) v dd 1.2 1.25 1.3 v supply voltages i/o (io_vdd) pll (pllp_vdd) pll (plla_vdd) v ddio 3.14 3.3 3.46 v input high voltage all pins v ih 2.0 ? v io_vdd +2v v note: all 3.3-v supplies must rise prior to the rise of the 1.25-v supplies to avoid a high current condition and possible system damage. input low voltage all pins v il ?0.3 ? 0.8 v input leakage current i in ?? 84 a clock pin input capacitance (extal) c in 4.7 pf high impedance (off-state) input current (@ 3.46v) i tsi ?10 ? 84 a output high voltage i oh = -5 ma xtal pin i oh = -10ma v oh 2.4 ? ? v output low voltage i ol = 5 ma xtal pin i ol = 10 ma v ol ?? 0.4v internal supply current 1 (core only) at internal clock of 150 mhz in normal mode i cci ? 65 100 ma in wait mode i ccw ?16 ?ma in stop mode 2 i ccs ?1.2 ?ma input capacitance c in ? ? 10 pf note: 1 the current consumption section provides a formula to compute the estimated current requirements in normal mode. in order to obtain these results, all inputs must be terminated (i.e., not allowed to float). measurements are based on synthetic intensive dsp benchmarks. the power consumption numbers in this specification are 90% of the measured results of this benchmark. this reflects typical dsp applications. typical internal supply current is measured with v core_vdd = 1.25v, v dd_io = 3.3v at t j = 25c. maximum internal supply current is measured with v core_vdd = 1.30v, v io_vdd) = 3.46v at t j = 115c. 2 in order to obtain these results, all inputs, which are not disconnected at stop mode, must be terminated (i.e., not allowed to float).
ac electrical characteristics dsp56374 data sheet, rev. 4.2 freescale semiconductor 29 9 ac electrical characteristics the timing waveforms shown in the ac electrical characteristics section are tested with a v il maximum of 0.8 v and a v ih minimum of 2.0 v for all pins. ac timing specifications, which are referenced to a device input signal, are measured in production with respect to the 50% point of the respective input signal?s transition. dsp56374 output levels are me asured with the production test machine v ol and v oh reference levels set at 1.0 v and 1.8 v, respectively. 10 internal clocks 11 external clock operation the dsp56374 system clock is derived from the on-chip oscillator or is externally supplied. to use the on-chip oscillator, connect a crys tal and associated resistor/capac itor components to extal and xtal; an example is shown below. table 18. internal clocks 1 no. characteristics symbol min typ max unit condition 1 comparison frequency fref 5 ? 20 mhz fref = fin/nr 2 input clock frequency fin fref*nr nr is input divider value 3 output clock frequency (with pll enabled) 2,3 fout tc 75 13.3 (ef mf x fm)/ (pdf df x od) 150 mhz ns fout=fvco/no where no is output divider value 4 output clock frequency (with pll disabled) 2,3 fout ? ef 150 mhz ? 5 duty cycle ? 40 50 60 % fvco=300mhz~600mhz note: 1 see users manual for definition. 2 df = division factor ef = external frequency mf = multiplication factor pdf = predivision factor fm= frequency multiplier od = output divider tc = internal clock period 3 maximum frequency will vary depending on the ordered part number.
dsp56374 data sheet, rev. 4.2 external clock operation freescale semiconductor 30 if the dsp56374 system clock is an externally supplie d square wave voltage source, it is connected to extal (figure 2.). when the external square wave s ource connects to extal, the xtal pin is not used. figure 2. external clock timing table 19. clock operation no. characteristics symbol min max units 6 extal input high 1 (40% to 60% duty cycle) eth 3.33 50 ns 7 extal input low 2 (40% to 60% duty cycle) etl 3.33 50 ns 8 extal cycle time with pll disabled with pll enabled etc 6.67 50 inf 200 ns 9 instruction cycle time= i cyc = t c 3 with pll disabled with pll enabled icyc 6.67 6.67 inf 13.33 ns suggested component values: f osc = 24.576 mhz r = 1 m 10% c (extal)= 18 pf calculations are for a 12 - 49 mhz crystal with the following parameters: shunt capacitance (c 0 ) of 10 pf - 12 pf series resistance 40 ohm c (xtal) = 47 pf drive level of 10 w extal v il v ih midpoint note: the midpoint is 0.5 (v ih + v il ). eth etl etc 7 8 6
external clock operation dsp56374 data sheet, rev. 4.2 freescale semiconductor 31 note: 1 measured at 50% of the input transition. 2 the indicated duty cycle is for the specified maximum frequency for which a part is rated. the minimum clock high or low time required for correct operation, however, remains the same at lower operating frequencies; therefore, when a lower clock frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time and low time requirements are met. 3 a valid clock signal must be applied to the extal pin within 3 ms of the dsp56374 being powered up. table 19. clock operation (continued) no. characteristics symbol min max units
dsp56374 data sheet, rev. 4.2 reset, stop, mode select, and interrupt timing freescale semiconductor 32 12 reset, stop, mode select, and interrupt timing table 20. reset, stop, mode select, and interrupt timing no. characteristics expression min max unit 10 delay from reset assertion to all pins at reset value 3 ? ? 11 ns 11 required reset duration 4 power on, external clock generator, pll disabled power on, external clock generator, pll enabled 2 xt c 13.4 ? ns 2 x t c 13.4 ? ns 13 syn reset deassert delay time minimum 2 t c 13.4 ? ns maximum (pll enabled) (2xt c )+t lock 5.0 ? ms 14 mode select setup time 10.0 ? ns 15 mode select hold time 10.0 ? ns 16 minimum edge-triggered interrupt request assertion width 2 xt c 13.4 ? ns 17 minimum edge-triggered interrupt request deassertion width 2 xt c 13.4 ? ns 18 delay from interrupt trigger to interrupt code execution 10 t c + 5 72 ? ns 19 duration of level sensitive irqa assertion to ensure interrupt service (when exiting stop) 1, 2, 3 pll is active during stop and stop delay is enabled (omr bit 6 = 0) 9+(128 t c ) 854 ? s pll is active during stop and stop delay is not enabled (omr bit 6 = 1) 25 t c 165 ? ns pll is not active during stop and stop delay is enabled (omr bit 6 = 0) 9+(128xt c ) + t lock 5.7 ms pll is not active during stop and stop delay is not enabled (omr bit 6 = 1) (25 x t c ) + t lock 5ms 20 delay from irqa , irqb , irqc , irqd , nmi assertion to general-purpose transfer output valid caused by first interrupt instruction execution 1 10 x t c + 3.0 69.0 ns
reset, stop, mode select, and interrupt timing dsp56374 data sheet, rev. 4.2 freescale semiconductor 33 figure 3. reset timing 21 interrupt requests rate 1 esai, esai_1, shi, timer 12 x t c ?80.0ns dma 8 x t c ?53.0ns irq , nmi (edge trigger) 8 x t c ?53.0ns irq (level trigger) 12 x t c ?80.0ns 22 dma requests rate data read from esai, esai_1, shi 6 x t c ?40.0ns data write to esai, esai_1, shi 7 x t c ?46.7ns timer 2 x t c ?13.4ns irq , nmi (edge trigger) 3 x t c ?20.0ns note: 1 when using fast interrupts and irqa , irqb , irqc , and irqd are defined as level-sensitive, timings 19 through 21 apply to prevent multiple interrupt service. to avoid these timing restrictions, the edge-triggered mode is recommended when using fast interrupts. long interrupts are recommended when using level-sensitive mode. 2 for pll disable, using external clock (pctl bit 16 = 1), no stabilization delay is required and recovery time will be defined by the omr bit 6 settings. for pll enable, (if bet 12 of the pctl register is 0), the pll is shutdown during stop. recovering from stop requires the pll to get locked. the pll lock procedure duration, pll lock cycles (plc), may be in the range of 0.5 ms. 3 periodically sampled and not 100% tested. 4 reset duration is measured during the time in which reset is asserted, v dd is valid, and the extal input is active and valid. when the v dd is valid, but the other ?required reset duration? conditions (as specified above) have not been yet met, the device circuitry will be in an uninitialized state that can result in significant power consumption and heat-up. designs should minimize this state to the shortest possible duration. table 20. reset, stop, mode select, and interrupt timing (continued) no. characteristics expression min max unit v ih reset reset value all pins 10 11 13
dsp56374 data sheet, rev. 4.2 reset, stop, mode select, and interrupt timing freescale semiconductor 34 figure 4. external fast interrupt timing figure 5. external interrupt timing (negative edge-triggered) figure 6. recovery from stop state using irqa interrupt service a) first interrupt instruction execution general purpose i/o irqa , irqb , irqc , irqd , nmi b) general purpose i/o irqa , irqb , irqc , irqd , nmi 18 19 20 irqa , irqb , irqc, irqd , nmi irqa , irqb , irqc, irqd , nmi 16 17 reset moda, modb, modc, modd, pinit v ih irqa , irqb , irqc ,irqd , nmi v ih v il v ih v il 14 15
serial host interface spi protocol timing dsp56374 data sheet, rev. 4.2 freescale semiconductor 35 13 serial host interface spi protocol timing table 21. serial host interface spi protocol timing no. characteristics 1,3,4 mode filter mode expression min max unit 23 minimum serial clock cycle = t spicc (min) master/slave bypassed 10.0 x t c + 9 76.0 ? ns very narrow 10.0 x t c + 9 76.0 ? ns narrow 10.0 x t c + 133 200.0 ? ns wide 10.0 x t c + 333 400.0 ? ns xx tolerable spike width on data or clock in. ? bypassed ? ? 0 ns very narrow ? ? 10 ns narrow ? ? 50 ns wide ? ? 100 ns 24 serial clock high period master bypassed ? 38.0 ? ns very narrow ? 38.0 ? ns narrow ? 100.0 ? ns wide ? 200.0 ? ns slave bypassed 2.0 x t c + 19.6 33.0 ? ns very narrow 2.0 x t c + 19.6 33.0 ? ns narrow 2.0 x t c + 86.6 100.0 ? ns wide 2.0 x t c + 186.6 200.0 ? ns 25 serial clock low period master bypassed ? 38.0 ? ns very narrow ? 38.0 ? ns narrow ? 100.0 ? ns wide ? 200.0 ? ns slave bypassed 2.0 x t c + 19.6 33.0 ? ns very narrow 2.0 x t c + 19.6 33.0 ? ns narrow 2.0 x t c + 86.6 100.0 ? ns wide 2.0 x t c + 186.6 200.0 ? ns 26 serial clock rise/fall time master slave ? ? ?? ? ? 5 ns ns ? ?
dsp56374 data sheet, rev. 4.2 serial host interface spi protocol timing freescale semiconductor 36 27 ss assertion to first sck edge cpha = 0 slave bypassed 2.0 x t c + 12.6 26 ? ns very narrow 2.0 x t c + 2.6 16 ? ns narrow 2.0 x t c ? 37.4 5 0?ns wide 2.0 x t c ? 87.4 5 0?ns cpha = 1 slave bypassed ? 10 ? ns very narrow ? 0 ? ns narrow ? 0 ? ns wide ? 0 ? ns 28 last sck edge to ss not asserted slave bypassed ? 12 ? ns very narrow ? 22 ? ns narrow ? 100 ? ns wide ? 200 ? ns 29 data input valid to sck edge (data input set-up time) master /slave bypassed ? 0 ? ns very narrow ? 0 ? ns narrow ? 0 ? ns wide ? 0 ? ns 30 sck last sampling edge to data input not valid master /slave bypassed 3.0 x t c 20 ? ns very narrow 3.0 x t c + 23.2 43.2 ? ns narrow 3.0 x t c + 53.2 73.2 ? ns wide 3.0 x t c + 80 100.0 ? ns 31 ss assertion to data out active slave ? ? 5 ? ns 32 ss deassertion to data high impedance 2 slave ? ? ? 9 ns 33 sck edge to data out valid (data out delay time) master /slave bypassed 3.0 x t c + 26.1 ? 46.2 ns very narrow 3.0 x t c + 90.4 ? 110.4 ns narrow 3.0 x t c + 116.4 ? 136.4 ns wide 3.0 x t c + 203.4 ? 223.4 ns 34 sck edge to data out not valid (data out hold time) master /slave bypassed 2.0 x t c 13.4 ? ns very narrow 2.0 x t c + 1.6 15 ? ns narrow 2.0 x t c + 41.6 55 ? ns wide 2.0 x t c + 91.6 105 ? ns 35 ss assertion to data out valid (cpha = 0) slave ? ? ? 12.0 ns table 21. serial host interface spi protocol timing (continued) no. characteristics 1,3,4 mode filter mode expression min max unit
serial host interface spi protocol timing dsp56374 data sheet, rev. 4.2 freescale semiconductor 37 36 sck edge following the first sck sampling edge to hreq output deassertion slave bypassed 3.0 x t c + 30 50 ? ns very narrow 3.0 x t c + 40 60 ? ns narrow 3.0 x t c + 80 100 ? ns wide 3.0 x t c + 120 150 ? ns 37 last sck sampling edge to hreq output not deasserted (cpha = 1) slave bypassed 4.0 x t c 57.0 ? ns very narrow 4.0 x t c 67.0 ? ns narrow 4.0 x t c 107.0 ? ns wide 4.0 x t c 157.0 ? ns 38 ss deassertion to hreq output not deasserted (cpha = 0) slave ? 3.0 x t c + 30 50.0 ? ns 39 ss deassertion pulse width (cpha = 0) slave ? 2.0 x t c 13.4 ? ns 40 hreq in assertion to first sck edge master bypassed 0.5 x t spicc + 3.0 x t c + 5 63 ? ns very narrow 0.5 x t spicc + 3.0 x t c + 5 63 ? ns narrow 0.5 x t spicc + 3.0 x t c + 5 125 ? ns wide 0.5 x t spicc + 3.0 x t c + 5 225 ? ns 41 hreq in deassertion to last sck sampling edge (hreq in set-up time) (cpha = 1) master ? ? 0 ? ns 42 first sck edge to hreq in not asserted (hreq in hold time) master ? ? 0 ? ns 43 hreq assertion width master ? 3.0 x t c 20 ? ns note: 1 v core_vdd = 1.2 5 0.05 v; t j = -40c to 110c (52 lqfp) / -40c to 105c (80 lqfp), c l = 50 pf 2 periodically sampled, not 100% tested 3 all times assume noise free inputs. 4 all times assume internal clock frequency of 150 mhz. 5 equation applies when the result is positive t c . table 21. serial host interface spi protocol timing (continued) no. characteristics 1,3,4 mode filter mode expression min max unit
dsp56374 data sheet, rev. 4.2 serial host interface spi protocol timing freescale semiconductor 38 figure 7. spi master timing (cpha = 0) ss (input) sck (cpol = 0) (output) sck (cpol = 1) (output) miso (input) valid mosi (output) msb valid lsb msb lsb hreq (input) 23 24 25 26 26 23 26 26 25 24 29 30 30 29 33 34 42 40 43
serial host interface spi protocol timing dsp56374 data sheet, rev. 4.2 freescale semiconductor 39 figure 8. spi master timing (cpha = 1) ss (input) sck (cpol = 0) (output) sck (cpol = 1) (output) miso (input) valid mosi (output) msb valid lsb msb lsb hreq (input) 23 24 25 26 26 23 26 26 25 24 29 29 30 33 34 42 40 41 30 43
dsp56374 data sheet, rev. 4.2 serial host interface spi protocol timing freescale semiconductor 40 figure 9. spi slave timing (cpha = 0) ss (input) sck (cpol = 0) (input) sck (cpol = 1) (input) miso (output) mosi (input) msb lsb msb lsb hreq (output) 23 24 25 26 26 23 26 26 25 24 35 31 33 34 29 30 38 36 34 32 valid valid 29 30 28 39 27
serial host interface (shi) i 2 c protocol timing dsp56374 data sheet, rev. 4.2 freescale semiconductor 41 figure 10. spi slave timing (cpha = 1) 14 serial host interface (shi) i 2 c protocol timing table 22. shi i 2 c protocol timing standard i 2 c no. characteristics 1,2,3,4,5 symbol/ expression standard fast-mode unit min max min max xx tolerable spike width on scl or sda filters bypassed very narrow filters enabled narrow filters enabled wide fileters enabled. ? ? ? ? ? 0 10 50 100 ? ? ? ? 0 10 50 100 ns ns ns ns 44 scl clock frequency f scl ? 100 ? 400 khz 44 scl clock cycle t scl 10 ? 2.5 ? s 45 bus free time t buf 4.7 ? 1.3 ? s 46 start condition set-up time t susta 4.7 ? 0.6 ? s ss (input) sck (cpol = 0) (input) sck (cpol = 1) (input) miso (output) mosi (input) msb lsb msb lsb hreq (output) 23 24 25 26 26 26 26 25 24 31 33 29 30 37 34 32 valid valid 29 28 27 33 30 36
dsp56374 data sheet, rev. 4.2 serial host interface (shi) i 2 c protocol timing freescale semiconductor 42 47 start condition hold time t hd;sta 4.0 ? 0.6 ? s 48 scl low period t low 4.7 ? 1.3 ? s 49 scl high period t high 4.0 ? 1.3 ? s 50 scl and sda rise time t r ?5.0 ? 5.0ns 51 scl and sda fall time t f ?5.0 ? 5.0ns 52 data set-up time t su;dat 250 ? 100 ? ns 53 data hold time t hd;dat 0.0 ? 0.0 0.9 s 54 dsp clock frequency filters bypassed very narrrow filters enabled narrow filters enabled wide filters enabled f osc 10.6 10.6 11.8 13.1 ? ? ? ? 28.5 28.5 39.7 61.0 ? ? ? ? mhz mhz mhz mhz 55 scl low to data out valid t vd;dat ?3.4 ? 0.9 s 56 stop condition setup time t su;sto 4.0 ? 0.6 ? s 57 hreq in deassertion to last scl edge (hreq in set-up time) t su;rqi 0.0 ? 0.0 ? ns 58 first scl sampling edge to hreq output deassertion 2 filters bypassed very narrow filters enabled narrow filters enabled wide filters enabled t ng;rqo 4 t c + 30 4 t c + 50 4 t c + 130 4 t c + 230 ? ? ? ? 57.0 77.0 157.0 257.0 ? ? ? ? 57.0 67.0 157.0 257.0 ns ns ns ns 59 last scl edge to hreq output not deasserted 2 filters bypassed very narrow filters enabled narrow filters enabled wide filters enabled t as;rqo 2 t c + 30 2 t c + 40 2 t c + 80 2 t c + 130 44 54 94 144 ? ? ? ? 44 54 94 144 ? ? ? ? ns ns ns ns 60 hreq in assertion to first scl edge filters bypassed very narrow filters enabled narrow filters enabled wide filters enabled t as;rqi 4327 4317 4282 4227 ? ? ? ? 927 917 877 827 ? ? ? ? ns ns ns ns 61 first scl edge to hreq is not asserted (hreq in hold time.) t ho;rqi 0.0 ? 0.0 ? ns table 22. shi i 2 c protocol timing (continued) standard i 2 c no. characteristics 1,2,3,4,5 symbol/ expression standard fast-mode unit min max min max
programming the serial clock dsp56374 data sheet, rev. 4.2 freescale semiconductor 43 15 programming the serial clock the programmed serial clock cycle, t i 2 ccp , is specified by the value of the hdm[7:0] and hrs bits of the hckr (shi clock control register). the expression for t i 2 ccp is t i 2 ccp = [t c 2 (hdm[7:0] + 1) (7 (1 ? hrs) + 1)] eqn. 1 where ? hrs is the prescaler rate select bit. when hrs is cleared, the fixed divide-by-eight prescaler is operational. wh en hrs is set, the prescaler is bypassed. ? hdm[7:0] are the divider modulus select bits. a divide ratio from 1 to 256 (hdm[7:0] = $00 to $ff) may be selected. in i 2 c mode, the user may select a value for the programmed serial clock cycle from 6 t c (if hdm[7:0] = $02 and hrs = 1) eqn. 2 to 4096 t c (if hdm[7:0] = $ff and hrs = 0) eqn. 3 the programmed serial clock cycle (t i 2 ccp ) should be chosen in order to achieve the desired scl serial clock cycle (t scl ), as shown in table 23 . note: 1 v core_vdd = 1.2 5 0.05 v; t j = -40c to 110c (52 lqfp) / -40c to 105c (80 lqfp), c l = 50 pf 2 pull-up resistor: r p (min) = 1.5 kohm 3 capacitive load: c b (max) = 50 pf 4 all times assume noise free inputs 5 all times assume internal clock frequency of 150mhz table 23. scl serial clock cycle (t scl ) generated as master nominal t i 2 ccp + 3 t c + 45ns + t r table 22. shi i 2 c protocol timing (continued) standard i 2 c no. characteristics 1,2,3,4,5 symbol/ expression standard fast-mode unit min max min max
dsp56374 data sheet, rev. 4.2 enhanced serial audio interface timing freescale semiconductor 44 figure 11. i 2 c timing 16 enhanced serial audio interface timing table 24. enhanced serial audio interface timing no. characteristics 1, 2, 3 symbol expression 3 min max condition 4 unit 62 clock cycle 5 t ssicc 4 t c 4 t c 26.4 26.4 ? ? x ck i ck ns 63 clock high period for internal clock t ssicch 2 t c ? 0.5 12.8 ? ns for external clock 2 t c 13.4 ? 64 clock low period for internal clock t ssiccl 2 t c 13.4 ? ns for external clock 2 t c 13.4 ? 65 sckr edge to fsr out (bl) high ? ? ? ? 17.0 7.0 x ck i ck a ns 66 sckr edge to fsr out (bl) low ? ? ? ? 17.0 7.0 x ck i ck a ns 67 sckr edge to fsr out (wr) high 6 ??? ? 19.0 9.0 x ck i ck a ns 68 sckr edge to fsr out (wr) low 6 ??? ? 19.0 9.0 x ck i ck a ns 69 sckr edge to fsr out (wl) high ? ? ? ? 16.0 6.0 x ck i ck a ns start scl hreq sda ack msb lsb stop 44 stop 46 49 48 50 51 53 52 45 58 55 56 61 47 60 57 59
enhanced serial audio interface timing dsp56374 data sheet, rev. 4.2 freescale semiconductor 45 70 sckr edge to fsr out (wl) low ? ? ? ? 17.0 7.0 x ck i ck a ns 71 data in setup time before sckr (sck in synchronous mode) edge ??12.0 19.0 ? ? x ck i ck ns 72 data in hold time after sckr edge ? ? 3.5 9.0 ? ? x ck i ck ns 73 fsr input (bl, wr) high before sckr edge 6 ??2.0 12.0 ? ? x ck i ck a ns 74 fsr input (wl) high before sckr edge ? ? 2.0 12.0 ? ? x ck i ck a ns 75 fsr input hold time after sckr edge ? ? 2.5 8.5 ? ? x ck i ck a ns 76 flags input setup before sckr edge ? ? 0.0 19.0 ? ? x ck i ck s ns 77 flags input hold time after sckr edge ? ? 6.0 0.0 ? ? x ck i ck s ns 78 sckt edge to fst out (bl) high ? ? ? ? 18.0 8.0 x ck i ck ns 79 sckt edge to fst out (bl) low ? ? ? ? 20.0 10.0 x ck i ck ns 80 sckt edge to fst out (wr) high 6 ??? ? 20.0 10.0 x ck i ck ns 81 sckt edge to fst out (wr) low 6 ??? ? 22.0 12.0 x ck i ck ns 82 sckt edge to fst out (wl) high ? ? ? ? 19.0 9.0 x ck i ck ns 83 sckt edge to fst out (wl) low ? ? ? ? 20.0 10.0 x ck i ck ns 84 sckt edge to data out enable from high impedance ??? ? 22.0 17.0 x ck i ck ns 85 sckt edge to transmitter #0 drive enable assertion ??? ? 17.0 11.0 x ck i ck ns 86 sckt edge to data out valid ? ? ? ? 18.0 13.0 x ck i ck ns 87 sckt edge to data out high impedance 7 ??? ? 21.0 16.0 x ck i ck ns table 24. enhanced serial audio interface timing (continued) no. characteristics 1, 2, 3 symbol expression 3 min max condition 4 unit
dsp56374 data sheet, rev. 4.2 enhanced serial audio interface timing freescale semiconductor 46 88 sckt edge to transmitter #0 drive enable deassertion 7 ??? ? 14.0 9.0 x ck i ck ns 89 fst input (bl, wr) setup time before sckt edge 6 ??2.0 18.0 ? ? x ck i ck ns 90 fst input (wl) setup time before sckt edge ??2.0 18.0 ? ? x ck i ck ns 91 fst input hold time after sckt edge ? ? 4.0 5.0 ? ? x ck i ck ns 92 fst input (wl) to data out enable from high impedance ???21.0?ns 93 fst input (wl) to transmitter #0 drive enable assertion ???14.0?ns 94 flag output valid after sckt rising edge ? ? ? ? 14.0 9.0 x ck i ck ns 95 hckr/hckt clock cycle ? 2 x t c 13.4 ? ns 96 hckt input edge to sckt output ? ? ? 18.0 ns 97 hckr input edge to sckr output ? ? ? 18.0 ns note: 1 v core_vdd = 1.25 0.05 v; t j = -40c to 110c (52 lqfp) / -40c to 105c (80 lqfp), c l = 50 pf 2 i ck = internal clock x ck = external clock i ck a = internal clock, asynchronous mode (asynchronous implies that sckt and sckr are two different clocks) i ck s = internal clock, synchronous mode (synchronous implies that sckt and sckr are the same clock) 3 bl = bit length wl = word length wr = word length relative 4 sckt(sckt pin) = transmit clock sckr(sckr pin) = receive clock fst(fst pin) = transmit frame sync fsr(fsr pin) = receive frame sync hckt(hckt pin) = transmit high frequency clock hckr(hckr pin) = receive high frequency clock 5 for the internal clock, the external clock cycle is defined by icyc and the esai control register. 6 the word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync signal waveform, but spreads from one serial clock before first bit clock (same as bit length frame sync signal), until the one before last bit clock of the first word in frame. 7 periodically sampled and not 100% tested. 8 esai_1 specs match those of esai. table 24. enhanced serial audio interface timing (continued) no. characteristics 1, 2, 3 symbol expression 3 min max condition 4 unit
enhanced serial audio interface timing dsp56374 data sheet, rev. 4.2 freescale semiconductor 47 figure 12. esai transmitter timing last bit see note sckt (input/output) fst (bit) out fst (word) out data out transmitter #0 drive enable fst (bit) in fst (word) in flags out note: in network mode, output flag transitions can occur at the start of each time slot within the frame. in normal mode, the output flag state is asserted for the entire frame period. figure 12 is drawn assuming positive polarity bit clock (tckp=0) and positive frame sync polarity (tfsp=0). first bit 62 64 78 79 83 84 88 87 87 85 92 89 86 94 90 91 93 94 95 63
dsp56374 data sheet, rev. 4.2 enhanced serial audio interface timing freescale semiconductor 48 figure 13. esai receiver timing sckr (input/output) fsr (bit) out fsr (word) out data in fsr (bit) in fsr (word) in flags in last bit first bit 62 64 65 69 70 72 71 75 73 74 75 77 76 63 66 note: figure 13 is drawn assuming positive polarity bit clock (rckp=0) and positive frame sync polarity (rfsp=0).
timer timing dsp56374 data sheet, rev. 4.2 freescale semiconductor 49 figure 14. esai hckt timing figure 15. esai hckr timing 17 timer timing figure 16. tio timer event input restrictions table 25. timer timing no. characteristics expression 150 mhz unit min max 98 tio low 2 t c + 2.0 15.4 ? ns 99 tio high 2 t c + 2.0 15.4 ? ns note: v core_vdd = 1.25 v 0.05 v; t j = -40c to 110c (52 lqfp) / -40c to 105c (80 lqfp), c l = 50 pf hckt sckt (output) 96 95 note: figure 14 is drawn assuming positive polarity high frequenc y clock (thckp=0) and positive bit clock polarity (tckp=0). hckr sckr (output) 97 95 note: figure 15 is drawn assumi ng positive polarity high frequency clock (rhckp=0) and positive bit clock polarity (rckp=0). tio 99 98
dsp56374 data sheet, rev. 4.2 gpio timing freescale semiconductor 50 18 gpio timing figure 17. gpio timing 19 jtag timing table 26. gpio timing no. characteristics 1 expression min max unit 100 extal edge to gpio out valid (gpio out delay time) 2 ?7ns 101 extal edge to gpio out not valid (gpio out hold time) 2 ?7ns 102 gpio in valid to extal edge (gpio in set-up time) 2 2?ns 103 extal edge to gpio in not valid (gpio in hold time) 2 0?ns 104 minimum gpio pulse high width t c + 13 19.7 ? ns 105 minimum gpio pulse low width t c + 13 19.7 ? ns 106 gpio out rise time ? ? 13.0 ns 107 gpio out fall time ? ? 13.0 ns note: 1 v core_vdd = 1.25 v 0.05 v; t j = -40c to 110c (52 lqfp) / -40c to 105c (80 lqfp), c l = 50 pf 2 pll disabled, extal driven by a square wave. table 27. jtag timing no. characteristics all frequencies unit min max 108 tck frequency of operation (1/(t c 3); maximum 10 mhz) ? 10.0 mhz valid gpio (input) gpio (output) extal 100 101 102 103 gpio (output) 104 105 106 107
jtag timing dsp56374 data sheet, rev. 4.2 freescale semiconductor 51 figure 18. test clock input timing diagram 109 tck cycle time in crystal mode 100.0 ? ns 110 tck clock pulse width measured at 1.65 v 50.0 ? ns 111 tck rise and fall times ? 3.0 ns 112 boundary scan input data setup time 15.0 ? ns 113 boundary scan input data hold time 24.0 ? ns 114 tck low to output data valid ? 40.0 ns 115 tck low to output high impedance ? 40.0 ns 116 tms, tdi data setup time 5.0 ? ns 117 tms, tdi data hold time 25.0 ? ns 118 tck low to tdo data valid ? 44.0 ns 119 tck low to tdo high impedance ? 44.0 ns note: 1. v core_vdd = 1.25 v 0.05 v; t j = -40c to 110c (52 lqfp) / -40c to 105c (80 lqfp), c l = 50 pf 2. all timings apply to once module data transfers because it uses the jtag port as an interface. table 27. jtag timing (continued) no. characteristics all frequencies unit min max tck (input) v m v m v ih v il 109 110 110 111 111
dsp56374 data sheet, rev. 4.2 jtag timing freescale semiconductor 52 figure 19. debugger port timing diagram figure 20. test access port timing diagram tck (input) data inputs data outputs data outputs data outputs vih vil input data valid output data valid output data valid 113 112 114 115 114 tck (input) tdi (input) tdo (output) tdo (output) tdo (output) vih vil input data valid output data valid output data valid tms 116 117 118 119 118
watchdog timer timing dsp56374 data sheet, rev. 4.2 freescale semiconductor 53 20 watchdog timer timing table 28. watchdog timer timing no. characteristics expression min max unit 120 delay from time-out to fall of tio1 2 t c 13.4 ? ns 121 delay from timer clear to rise of tio1 2 x tc 13.4 ? ns
dsp56374 data sheet, rev. 4.2 watchdog timer timing freescale semiconductor 54 appendix a package information a.1 dsp56374 pinout figure a-1. 80-pin vdd connections 60 sdo5_1_pe6 59 sdo4_1_pe7 58 sdo3_pc8 57 sdo2_pc9 56 sdo1_pc10 55 sdo0_pc11 54 sdo3_1_pe8 53 sdo2_1_pe9 52 core_vdd 51 core_gnd 50 sdo1_1_pe10 49 sdo0_1_pe11 48 pinit_nmi 47 io_vdd 46 xtal 45 extal 44 plld_vdd 43 plld_gnd 42 pllp_gnd 41 pllp_vdd io_vdd 21 gpio_pg6 22 gpio_pg5 23 tdo 24 tdi 25 tms 26 tck 27 gpio_pg4 28 tio00 29 wdt/tio1 30 plock/tio2 31 core_vdd 32 core_gnd 33 gpio_pg3 34 reset_b 35 gpio_pg2 36 gpio_pg1 37 gpio_pg0 38 plla_vdd 39 plla_gnd 40 io_vdd 1 moda_irqa_ph0 2 modb_irqb_ph1 3 gpio_pg13 4 gpio_pg12 5 modc_irqc_ph2 6 modd_irqd_ph3 7 gpio_pg11 8 core_vdd 9 core_gnd 10 gpio_pg10 11 gpio_pg9 12 hreq_ph4 13 ss_ha2 14 sck_scl 15 miso_sda 16 mosi_ha0 17 gpio_pg8 18 gpio_pg7 19 io_gnd 20 80 io_gnd 79 sdo5_pc6 78 sdo4_pc7 77 fsr_1_pe1 76 fsr_pc1 75 fst_pc4 74 fst_1_pe4 73 gpio_pg14 72 core_vdd 71 core_gnd 70 sckr_1_pe0 69 sckr_pc0 68 sckt_pc3 67 sckt_1_pe3 66 hckr_1_pe2 65 hckr_pc2 64 hckt_pc5 63 hckt_1_pe5 62 scan 61 io_vdd 1.25 v 3.3 v filter
watchdog timer timing dsp56374 data sheet, rev. 4.2 freescale semiconductor 55 figure a-2. 52-pin vdd connections 39 sdo3_pc8 38 sdo2_pc9 37 sdo1_pc10 36 sdo0_pc11 35 core_vdd 34 core_gnd 33 pinit_nmi 32 xtal 31 extal 30 plld_vdd 29 plld_gnd 28 pllp_gnd 27 pllp_vdd io_vdd 14 tdo 15 tdi 16 tms 17 tck 18 tio00 19 wdt/tio1 20 plock/tio2 21 core_vdd 22 core_gnd 23 reset_b 24 plla_vdd 25 plla_gnd 26 io_vdd 1 moda_irqa_ph0 2 modb_irqb_ph1 3 modc_irqc_ph2 4 modd_irqd_ph3 5 core_vdd 6 core_gnd 7 hreq_ph4 8 ss_ha2 9 sck_scl 10 miso_sda 11 mosi_ha0 12 io_gnd 13 52 io_gnd 51 sdo5_pc6 50 sdo4_pc7 49 fsr_pc1 48 fst_pc4 47 core_vdd 46 core_gnd 45 sckr_pc0 44 sckt_pc3 43 hckr_pc2 42 hckt_pc5 41 scan 40 io_vdd 1.25 v 3.3 v filter
dsp56374 data sheet, rev. 4.2 watchdog timer timing freescale semiconductor 56 a.2 package information a.2.1 80-pin package .
watchdog timer timing dsp56374 data sheet, rev. 4.2 freescale semiconductor 57
dsp56374 data sheet, rev. 4.2 watchdog timer timing freescale semiconductor 58
watchdog timer timing dsp56374 data sheet, rev. 4.2 freescale semiconductor 59 .
dsp56374 data sheet, rev. 4.2 watchdog timer timing freescale semiconductor 60 a.2.2 52-pin package
watchdog timer timing dsp56374 data sheet, rev. 4.2 freescale semiconductor 61
dsp56374 data sheet, rev. 4.2 watchdog timer timing freescale semiconductor 62
watchdog timer timing dsp56374 data sheet, rev. 4.2 freescale semiconductor 63
dsp56374 rev. 4.2, 1/2007 how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2004, 2005, 2006, 2007. all rights reserved.

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